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v1.1 data sheet 1 2002-07 abs system ic tle 6210 tle 6211 p -dso-20-10, -12, -16 1overview 1.1 features ? 5 v, 800 ma linear regulator undervoltage/overvoltage reset undervoltage and overvoltage logout digital watchdog supervision for 2 microcontrollers (motor) relay driver (valve) relay driver inverted or non inverted lamp relay driver enable output overtemperature and overcurrent protection 1.2 functional description the tle 6210 and tle 6211 are integrated circuit consisting of a 5 v voltage regulator with 800 ma current capability, different relay driver outputs and supervision logic. the supervision logic watches the input voltage and the regulator output voltage both for over-voltage and under-voltage. in addition two window watchdogs supervise the correct operation of 2 independent watchdog signals, e.g. from two microcontrollers. the tle 6210 and tle 6211 are designed especially for the severe conditions of abs/ asr applications in an automotive environment. type ordering code package/shipment tle 6210 c on request bare dice tle 6210 g on request p-dso-20-12, tape and reel tle 6211 g on request p-dso-20-12, tape and reel
tle 6210 tle 6211 overview v1.1 data sheet 2 2002-07 1.3 block diagram figure 1 block diagram linear regulator reset detection uzp uvlo and ovlo detection usts under- and overvoltage reset detection tle6210-block ad 20.09.01 ust usts uzp gnd res1 res2 en pgnd window watchdog sia mra wd1 wd 2 oscillator clock super- vision charge pump ucp supervisionlogic pgnd sila pgnd nsila pgnd mr pgnd vr
tle 6210 tle 6211 pin / pad configuration v1.1 data sheet 3 2002-07 2 pin / pad configuration figure 2 pin configuration p-dso-20-12 figure 3 chip-layout 110 11 20 layout vr nsila gndp sila gndp gnd mr res2 en res1 ucp uzp sia wd2 mra wd1 gnd usts ust
tle 6210 tle 6211 pin / pad configuration v1.1 data sheet 4 2002-07 pin / pad definitions and functions pin number symbol / pad name function tle 6210 g tle 6211g 11gnd power gnd connection 22n.c. not connected 33 u zp supply voltage ; reverse protection diode is required 44 u cp charge pump capacitor pin; an external capacitor is the energy storage for the charge pump 55res1 reset output 1 ; open collector output with integrated pull-up resistor. a high indicates normal operation; function identical to res2 66en enable output ; open collector; low indicates an error condition 77res2 reset output 2 ; open collector output with integrated pull-up resistor. a high indicates normal operation; function identical to res1 88vr valve relay output ; open drain output 9?sila lamp output ; open drain output; for tle 6210 cw only ?9nsila inverted lamp output ; open drain output; for tle 6211 cw only 10 10 gnd power ground connection 11 11 gnd power ground connection 12 12 mr motor relay output ; open drain output 13 13 sia lamp control signal input ; controls sila/nsila; a logic high switches sila off and nsila on 14 14 wd2 watchdog input 2 15 15 mra motor relay control input ; a logic high switches mr on 16 16 wd1 watchdog input 1 17 17 gnd logic ground 18 18 u sts sense input for u st supervision 19 19 u st 5 v linear regulator output 20 20 gnd ground connection backside metallization gnd the lead frame connects the pins 1, 10, 11 and 20 to the backside metallization.
tle 6210 tle 6211 electrical characteristics v1.1 data sheet 5 2002-07 3 electrical characteristics 3.1 absolute maximum ratings -40 c t j 150 c # parameter symbol limit values unit conditions min. max. m1 supply voltage u zp 020v? 026.5v 0 < t p 5 min.; -40 c 80 c 035v 0 < t p 200 ms; f < 0.067 hz; n 360 cycles 035v 0 < t p 50 ms; 0 < f p 1 hz; n 36000 cycles -1.5 ? v t p = 2 s m2 supply voltage variation d u zp /d t ? 10 v/ s? m3 output voltage at vr, mr u vr , u mr ? 60 v vr, mr-dmos off m4 output voltage at sila u sila ? 42 v sila-dmos off m5 output voltage at nsila u nsila ? 42 v nsila-dmos off m6 output voltage at res1, res2 u res1 u res2 -0.5 7 v ? m7 output voltage at en u en -0.5 7 v ? m8 input voltage at wd1, wd2, mra, sia u wd1 , u wd2 u mra , u sia -0.5 7 v ? m9 voltage u cp u cp -0.5 20 v ? m10 storage temperature t stg -55 150 c ? m11 junction temperature t j -40 150 175 c c continuos short term (< 50 h over lifetime)
tle 6210 tle 6211 electrical characteristics v1.1 data sheet 6 2002-07 note: stresses above the ones listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. m12 esd ? 4000 2000 ? ? v v according to eia/jesd 22-a 114b u zp , mr, en, vr, sila, all other pins m13 life time t b 10000 ? h ambient temperature range: -40c 2% -20c 10% 25c 24% 60c 34% 80c 24% 100c 5% >120c 1% 3.1 absolute maximum ratings (cont?d) -40 c t j 150 c # parameter symbol limit values unit conditions min. max.
tle 6210 tle 6211 electrical characteristics v1.1 data sheet 7 2002-07 within the functional range the device works according to the functional description. however parameters may exceed the values given in the characteristics. 3.2 functional range # parameter sym- bol limit values unit conditions min. typ. max. f1 supply voltage u zp 4.5 14.0 18 v ? ? ? 26.5 v t < 5 min. ??4.5v u st 0.3 v; reset = low; enable = low; vr and mr off f2 input capacitor c uzp 0.33 3.3 ? f t u = 20 c u n = 63 v typ. = mkt f3 f4 case temperature t c -40 ? 125 c p-dso-20-12 junction temperature t j -40 ? ? ? 150 175 c c life time short time 1) f5 thermal resistance junction-ambient r thja ? 40 ? k/w p-dso-20-12 minimum footprint f6 thermal resistance junction-case r thjc ? ? 2.4 k/w p-dso-20-12 1) parameter may deviate in the temperature range t j = 150 c ? 175 c total operation time max. 50 h for temperature range t j > 150 c
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 8 2002-07 4 block description and electrical characteristics 4.1 general 4.2 oscillator a 16 khz oscillator is used as time base for the 1 khz clock. an independent clock supervision circuit supervises the oscillator. if the oscillator clock is missing the error flag is set. characteristics 6 v u zp 18 v, -40 c t j +150 c, if not otherwise specified # parameter sym- bol limit values unit conditions min. typ. max. 4.1.1 power consumption regulator i uzp ?715ma u zp = 16 v, i ust = 800 ma, vr on, sila on, en, res1, res2 = high 4.1.2 overtemperature protection threshold t ab 150 ? ? c t j > t ab characteristics internal oscillator 6 v u zp 18 v, -40 c t j +150 c, if not otherwise specified # parameter sym- bol limit values unit conditions min. typ. max. 4.2.1 frequency f osz 14.4 13.6 16 ? 17.6 18.4 khz khz u zp 6 v 4.7 v u zp < 6 v 4.2.2 clock supervision t clue ? 120 ? s error if t low or t high > t clue 4.2.3 logic time base t clk 0.9 1 1.1 ms period
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 9 2002-07 4.3 charge pump the integrated charge pump requires an external capacitor at pin u cp . the charge pump voltage is typically 15 v. it is internally used for the voltage regulator only. it is only intended for internal function and may not be used for any external loads. the output voltage is short circuit protected against the supply voltage. characteristics charge pump 6 v u zp 18 v, -40 c t j +150 c, if not otherwise specified # parameter sym- bol limit values unit conditions min. typ. max. 4.3.1 power up time t cp ?10? ms u zp = 6 v; c cp = 68 nf; load capacitor to u =0.9 u cpmax 4.3.2 charge pump voltage u cp ? 15 22 v regulator on 4.3.3 frequency f cp 1.4 3.2 ? mhz ?
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 10 2002-07 4.4 voltage regulator the 5 v low drop linear regulator can supply up to 800 ma current. the regulator requires an output capacitor. the linear regulator is equipped with overcurrent protection and its own overtemperature protection. the linear element consists of 2 anti-serial dmos transistors. in case of low input supply voltage this avoids discharging of the output capacitor. the output voltage u st is supervised for over- and undervoltage. u st output has to be connected externally to the sense input u sts . if over- or undervoltage condition is detected the reset outputs res1 and res2 are logical low. for a detailed description of the reset logic please see chapter 4.9 . characteristics voltage regulator 6 v u zp 18 v, -40 c t j +150 c, if not otherwise specified # parameter sym- bol limit values unit conditions min. typ. max. 4.4.1 nominal output voltage u st 4.95 4.925 5.00 5.00 5.05 5.075 v v u z p = 14 v; i st = 400 ma; output capacitor as defined in 4.4.11 ; on wafer level t j = 25 c p-dso-20-12 4.4.2 u st load current i st ? ? 800 ma ? 4.4.3 line variation u st ?? 50 mv t j = 25 c ; 6.0 v u zp 18 v; i st = 600 ma; capacitor as defined in 4.4.11 ; d u z /d t < 1 v/ s
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 11 2002-07 4.4.4 load variation u st ?? 50 mv t j = 25 c ; u z p = 14 v; 0 ma i st 800 ma; capacitor as defined in 4.4.11 ; d i st /d t 1 ma/ s 4.4.5 temperature variation u st ? 50 100 mv u z p = 14 v; i st = i stmax ; -40 c t j 150 c; capacitor as defined in 4.4.11 ; for die mounted in a hybrid: d t u /d t 10 k/s for p-dso-20-12: d t g /d t 5 k/min. 4.4.6 long time drift u st ? ? ? ? 50 tbd mv mv u zp u zpmax. ; 0 ma i st i stmax. ; -40 c t j 150 c; t b = 5000 h t b = 10000 h 4.4.7 overall output voltage tolerance u st 4.75 5.00 5.25 v all parameters from 4.4.1 to 4.4.6 4.4.8 power supply ripple rejection u stss ?? 25 mv 0 hz f ust 10 khz; capacitor as defined in 4.4.11 ; 7 v u zp 24 v 4.4.9 series resistor r dson ? ? ? ? 1.7 2.7 t j = 25 c t j = 150 c u cp > 15 v; u zp = 6 v; i st = 800 ma 4.4.10 maximum output current (output shorted) i k 0.8 ? 1.6 a u cp > 15 v; u st = 0 v; 4.5 v u zp 18 v 4.4.11 load capacitor at output u st c ust 3.3 ? 150 f t u = 20 c; u n = 25 v; type etqw roederstein z ?4? f = 100 khz; t u = 20 c 4.4.12 u st off voltage u strest ? ? 400 mv i st = 0 ma 4.4.13 clamping voltage u zst 5.5 ? 7 v clamping voltage at i = 100 ma characteristics voltage regulator (cont?d) 6 v u zp 18 v, -40 c t j +150 c, if not otherwise specified # parameter sym- bol limit values unit conditions min. typ. max.
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 12 2002-07 4.5 enable-output en the open collector enable output en informs the system about any error condition. any error except a detected supply under-voltage will set the en output low. of cause for long under-voltage at the supply line, soon the u st output capacitor will be discharged and this will cause u st under-voltage and therefore en low. the time depends on the load and the output capacitor. the en is an open collector output. it is short circuit protected to u st . after power up when the first watchdog edges at wd1 a wd2 are detected the enable output is switched into high state. characteristics en output 6 v u zp 18 v, -40 c t j +150 c, if not otherwise specified # parameter symbol limit values unit conditions min. typ. max. 4.5.1 output low voltage u l ? ? ? ? 0.4 0.2 v v i l 10 ma i l 1 ma 4.5.2 reverse current i r ??5 a u en = 5 v
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 13 2002-07 power driver the tle 6210/tle 6211 includes 3 open drain outputs for loads up to 0.5 a: the two drivers vr and mr are intended for (valve and motor) relays, while the sila/nsila output is designed for a lamp. in the tle 6210 gw the sila output is available. the output goes low if the supply voltage u zp is no longer available ? the dmos is switched on automatically. in the tle 6211 gw the nsila has the inverted polarity related to sila. in bare dice both outputs sila and nsila can be used. . 4.6 valve relay output vr the valve relay output vr is switched on after the power up reset and valid watchdog signals. the driver has an open drain configuration and can supply up to 500 ma. the output is protected against overtemperature and overcurrent. the output is short circuit protected to u z . the output stage is equipped with its own overtemperature protection. in case of overvoltage at the supply u zp the output is switched off. however the output is not protected against overvoltages caused by switching inductive loads. therefore externally a free wheeling diode is required as shown in the application diagram. the valve relay output vr is controlled by the internal supervision logic. if any watchdog errors or supply over-voltage is detected or the 5 v regulator is out of range, the vr is switched off (please see also table 1 on page 19 and table 2 on page 28 ). characteristics relay driver output vr 6 v u zp 18 v, -40 c t j +150 c, if not otherwise specified # parameter sym- bol limit values unit conditions min. typ. max. 4.6.1 saturation voltage u ds ??1.2v r last 35 ; i l 0.5 a; 6 v u zp 16 v 4.6.2 on state resistance r dson ??2.4 t j = 150 c; i l = 0.5 a; u zp = 6 v 4.6.3 overload detection current i k 500 ? ? ma ? 4.6.4 output leakage current i r ? ? ? ? 0.5 2 ma ma u a 16 v 16 v < u a 60 v 4.6.5 overtemperature shutdown threshold t k 150 ? ? c ?
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 14 2002-07 4.7 motor relay driver the motor relay driver mr is controlled by the mra input signal and the internal control logic. a logic high at the mra input switches the mr low side switch on, a logic low signal switches it off. however the supervision logic overrules the mra input condition. please see also table 1 on page 19 and table 2 on page 28 . the output is an open collector output and can sink up to 500 ma. it is protected against overtemperature and overcurrent and short circuit prove to u z . even the output is switched off by the supervision logic at u zp overvoltage externally a free wheeling diode is required to protect the output against switching off inductive loads. characteristics relay driver output mr 6 v u zp 18 v, -40 c t j +150 c, if not otherwise specified # parameter sym- bol limit values unit conditions min. typ. max. 4.7.1 saturation voltage u ds ??1.2v r last 35 ; i l 0.5 a; 6 v u zp 16 v 4.7.2 on state resistance r dson ??2.4 t j = 150 c; i l = 0.5 a; u zp = 6 v 4.7.3 overload detection current i k 500 ? ? ma ? 4.7.4 output leakage current i r ? ? ? ? 0.5 2 ma ma u a 16 v 16 v < u a 60 v 4.7.5 overtemperature shutdown threshold t k 150 ? ? c ?
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 15 2002-07 4.7.1 control input mra the logic inputs mra expect ttl-type signals from a -controller with 5 v i/os. an integrated pull-up resistor ensures that an open input is read high. characteristics control inputs mra 6 v u zp 18 v, -40 c t j +150 c, if not otherwise specified # parameter sym- bol limit values unit conditions min. typ. max. 4.7.6 internal pull-up resistor to u st r wd 10 20 40 k 0 v u e u st + 0.3 v 4.7.7 input voltage low u l -0.3 ? 1.0 v ? 4.7.8 input voltage high u h 2.0 ? u st + 1.0 v? 4.7.9 input current i h ?? 5 a u e = u st ??1.0ma u st < u e u st + 1 v
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 16 2002-07 4.8 error lamp output sila and lamp relay output nsila the sila output is a 300 ma open collector output. it is available in the tle 6210 g. sila is a self-on output: it is switched on if the supply voltage is missing. the tle 6211 g is equipped with the logically inverted nsila output. nsila is a 30 ma open collector output. it is intended to drive the lamp relay. in the dice version tle 6211 c both outputs can be used. both sila and nsila are intended to control a warning lamp. the output is controlled by the internal supervision logic and control signal at the sia pin. a logic high at the sia input switches sila off and nsila on. the supervision logic will switch on sila if a watchdog timing violation is detected or the output voltage u st is out of range. an u zp overvoltage will not effect nsila. table 1 on page 19 and table 2 on page 28 give an overview on the different errors. the sila output is equipped with its own overtemperature protection. characteristics lamp driver output sila 6 v u zp 18 v, -40 c t j +150 c, if not otherwise specified # parameter sym- bol limit values unit conditions min. typ. max. 4.8.1 saturation voltage u sila ? ? ? ? 2.5 2.5 v i = 300 ma; u z p 6 v i = 300 ma; u zp = 0 v 4.8.2 overload detection current i k 300??ma? 4.8.3 output leakage current i r ? ? ? ? 0.1 4 ma ma u sila 16 v 16 v < u sila < 42 v 4.8.4 threshold voltage for automatic on u zp 1?4.7v u sila 2.5 v; i = 300 ma 4.8.5 overtemperature shutdown threshold t k 150 ? ? c u zp 6 v
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 17 2002-07 4.8.1 control input sia the logic inputs sia expect ttl-type signals from a -controller with 5 v i/os. an integrated pull-up resistor ensures that an open input is read high. characteristics lamp-relay driver output nsila 6 v u zp 18 v, -40 c t j +150 c, if not otherwise specified # parameter sym- bol limit values unit conditions min. typ. max. 4.8.6 on state resistance r dson ??33 t j = 150 c; i = 30 ma; u zp 7 v 4.8.7 overload detection current i k 30??ma? 4.8.8 output leakage current i r ??10 a u nsila 42 v characteristics control inputs sia 6 v u zp 18 v, -40 c t j +150 c, if not otherwise specified # parameter sym- bol limit values unit conditions min. typ. max. 4.8.9 internal pull-up resistor to u st r wd 10 20 40 k 0 v u e u st + 0.3 v 4.8.10 input voltage low u l -0.3 ? 1.0 v ? 4.8.11 input voltage high u h 2.0 ? u st + 1.0 v? 4.8.12 input current i h ?? 5 a u e = u st ??1.0ma u st < u e u st + 1 v
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 18 2002-07 supervision the tle 6210 and tle 6211 are equipped with a complex supervision logic. the input voltage and the regulator output voltage is supervised. in addition two -controller are supervised by independent watchdog circuits. 4.9 overvoltage and undervoltage both the supply voltage u zp and the output voltage u st are supervised for over- and undervoltage. in case any undervoltage or overvoltage condition at u st or u zp is detected, the reset outputs res1 and res2 are switched to low state. res1 and res2 are not controlled by the watchdog logic. to supervise the output voltage u st an independent bandgap from the reference bandgap is used. the reset outputs res1 and res2 are together controlled by the u st reset logic and the supply undervoltage lockout (uvlo) and overvoltage lockout (ovlo). a logic high at the res1 and res2 indicates normal operation. the outputs are open collector type outputs with integrated pull-up resistors to u st . even when the u st voltage drops, the reset outputs res1 and res2 remain low (< 0.4 v). both undervoltage and overvoltage detection of u st and u zp use a voltage hysteresis to avoid any reset toggling. undervoltage and overvoltage detection u st the u st output voltage has to be externally connected to the u sts sense input. to be able to detect also wrong output voltages causes by a malfunction of the related bandgap reference for supervision an independent bandgap is used. as soon as any reset condition is detected the res1 and res2 go low. 4.9.1 undervoltage lockout (uvlo) and overvoltage lockout (ovlo) the supply voltage u zp is supervised as well. if the voltage rises above the upper threshold value of 19.5 v reset is asserted. when an undervoltage occurs, after some time the output voltage will drop below the reset threshold and a reset is asserted. the undervoltage lockout is only valid during power up. both the ovlo and the uvlo threshold use a hysteresis to avoid reset glitches. in addition the ovlo is digitally filtered. overvoltage below 2 to 3 clock cycles (equals typical 2 s or 3 s) are neglected to avoid resetting the system when any inductive load is switched off.
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 19 2002-07 when the undervoltage condition at u st or u zp is no longer detected a reset reaction time of typical 52 ms (52 clock cycles) is started. after this time the reset signal is set high. z: high impedance * in the application the voltage is undefined as regulator is off table 1 truth table overvoltage and undervoltage supervision the table assumes that no other error is detected, especially no watchdog failure and no clock failure. supply voltage u zp regulator voltage u st sila nsila mr vr en res 1 res 2 regulator ok ok = sia = not sia = not mra lzhon ok under- voltage lz zzll on normal over- voltage lz zzlh on under- voltage under- voltage lz zzz*l off under- voltage ok = sia = not sia not mra lhhon over- voltage x = l = not sia z z z* l off
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 20 2002-07 4.9.2 under- and overvoltage reset behavior figure 4 characteristics supervision of u zp , u st 6 v u zp 18 v, -40 c t j +150 c, if not otherwise specified # parameter symbol limit values unit conditions min. typ. max. u zp -undervoltage 4.9.1 u zp undervoltage threshold u zpu 5.2 5.3 5.4 v u st off 4.9.2 u zp undervoltage hysteresis u h 20 ? 50 mv u zpu(on) = u zpu(off) + u h 1) u zp -overvoltage 4.9.3 u zp overvoltage threshold u zue 18.75 19.5 20.25 v outputs nsila, vr, mr, u st off uzp 12v 5.3v t ust 5v 4.6v t t t r es1 r es2 52ms 5v 5v
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 21 2002-07 4.9.4 u zp overvoltage hysteresis u h 0.5 ? 1.0 v u h = u zue(on) - u zue(off) 4.9.5 u zp overvoltage filter t on 2 1.8 ? ? 3 3.4 t clk ms u zp overvoltage threshold t off 2 1.8 ? ? 3 3.4 t clk ms u zp < overvoltage threshold u st -undervoltage 4.9.6 u st undervoltage threshold u stu 4.5 4.6 4.7 v res1, res2 = low 4.9.7 u st undervoltage hysteresis u h 20 ? 50 mv u stu(on) = u stu(off) + u h 1) u st -overvoltage 4.9.8 u st overvoltage threshold u stue 5.3 5.4 5.5 v error flag is set 4.9.9 u st overvoltage hysteresis u h 20 ? 50 mv u stue(on) = u stue (off) - u h 1) 4.9.10 u sts input current i sts 0.94 1.5 2.2 ma u sts = 6 v 4.9.11 reset delay time t rh ? 46.35 52 52 ? 58.85 t clk ms u zp 5.4 v u st 4.75 v 1) hysteresis guaranteed by design. characteristics supervision of u zp , u st (cont?d) 6 v u zp 18 v, -40 c t j +150 c, if not otherwise specified # parameter symbol limit values unit conditions min. typ. max.
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 22 2002-07 4.10 reset outputs res1, res2 the two reset outputs res1 and res2 are open collector outputs with integrated pull- up resistor of typical 10 k to u st . both outputs are protected against short circuits to u st . characteristics supervision of res1 and res2 6 v u zp 18 v, -40 c t j +150 c, if not otherwise specified # parameter sym- bol limit values unit conditions min. typ. max. 4.10.1 output low voltage u l ? ? ? ? 0.4 0.4 v v i l = 0.8 ma; u st = 1.8 v i l = 2 ma; u st = 4.5 v 1.8 v u st 4.5 v 4.10.2 output high voltage u h u st - 0.1 ? u st v r l 10 m 4.10.3 internal pull-up resistor to u st r res 51020 k 0 v u a u st + 0.3 v
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 23 2002-07 4.11 watchdog to supervise the operation of 2 -processors watchdog logic for two input signals is integrated. the logic expects at each wd1 and wd2 rectangular signals with 10 ms high and 10 ms low time. deviations from the expected time are counted as errors and influence the output signals. a digital filter suppresses noise or pulses below 3 clock cycles (typ. 3 ms). the detection ciruit is described in figure 12 . after power up and 1or 2 valid watchdog edges the wd logic enables the output drivers. figure 5 enable output en after correct watchdog signals at wd1 and wd2 are present; wd1 and wd2 start with logic low figure 6 enable output en after correct watchdog signals at wd1 and wd2 are present; wd1 and wd2 start with logic high 1 0 1 0 1 0 wd1 wd2 en 12 10ms 3* t clk after the 2nd wd-edge (falling edge) wd-start-up-with low ad 04/02 1 0 1 0 1 0 wd1 wd2 en 12 3 * t clk after 1st. wd edge 10ms wd-start-up-with high ad 04/02
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 24 2002-07 the logic expects the time between two clock edges between 3 and 15 clock-cycles. if this window is not met, the outputs vr, mr and nsila are switched off, sila is switched on and the enable output goes low. an internal counter ( see figure 12 ) includes a 4 bit counter. each time the value 15 is reached a dominant counter reset signal is generated at the output "=15". this pulse is generated continuously at t = (15+3) t1 + n * (16*t1) after the last valid watchdog pulse was detected. when internal resets and watchdog edges occur at the same time, the internal reset is dominant. figure 7 missing watchdog signals cause en low 1 0 1 0 1 0 15* t clk + delay = 15* t clk + 3* t clk 10ms wd1 wd2 en delay (3* t clk ) t > 16 *t clk wd-controls-en-2 ad 04/02
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 25 2002-07 figure 8 missing watchdog signals cause en low figure 9 timing diagram - any watchdog signal missing causes a high signal at the output "=15" (counter reset). this signal sets back the logic 1 0 1 0 1 0 15*t clk + delay = 15*t clk + 3* t clk wd1 wd2 en delay (3* t clk ) t < 15 *t clk delay (3* t clk ) 15*t clk wd-controls-en ad 03/02 10ms 1 0 1 0 1 0 10ms wd1 wd2 en wd signal not detected (15+3) * t clk 1 0 counter reset 16* t clk wd-missing ad 03/02
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 26 2002-07 any watchdog high or low time above 15 ms influences the enable (en) and the vr output.if the time after the last watchdog edge exceeds 120 clock cycles - typical 120 ms- an error flag is set. this flag can only be removed by powering down the ic. figure 10 missing watchdog signals for more than 120 * t clk (typ. 120ms) sets the failure register an integrated pull-up resistor to u st in the wd1 and wd2 inputs ensures to detect a permanent logic high in case the input is open. 1 0 1 0 1 0 10ms wd1 wd2 en (15+3) * t clk 1 0 112 * t clk + delay = 112 * t clk + 3 * t clk ) counter reset 16 * t clk 1 0 set error flag set-error-flag ad 03/02
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 27 2002-07 characteristics wd1, wd2 6 v u zp 18 v, -40 c t j +150 c, if not otherwise specified # parameter sym- bol limit values unit conditions min. typ. max. 4.11.1 internal pullup resistor to u st r wd 10 20 40 k 0 v u e u st + 0.3 v 4.11.2 input voltage low u l -0.3 ? 1.0 v ? 4.11.3 input voltage high u h 2.0 ? u st + 1.0 v? 4.11.4 input current i h ?? 5 a u e = u st ??1.0ma u st < u e u st + 1 v characteristics watchdog 6 v u zp 18 v, -40 c t j +150 c, if not otherwise specified # parameter sym- bol limit values unit conditions min. typ. max. 4.11.5 release reaction time t on 1? 2 t clk number of valid watchdog input clock edges 4.11.6 closed window time t pulse ? 2.25 1.8 3 3 3 ? 3.3 3.3 t clk ms ms the distance between clock edges is at least t pulse equals: periodically pulse 4.11.7 open window time t vr ? 13.5 15 15 ? 17.6 t clk ms if the edge distance t > t vr , vr is switched off equals 4.11.8 error flag detection t fsp ? 108 120 120 ? 132 t clk ms if t > t fsp , the error flag is set. equals
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 28 2002-07 4.11.1 watchdog logic table 2 and figure 11 show the watchdog logic. figure 12 shows the logic implementation z: high impedance watchdog wd1, wd2 time between edges clock sila nsila mr vr en res1/2 error flag ok ok = sia = not sia = not mra lzh l < 3 * t clk ok l z z z l h l > 15 * t clk ok l z z z l h l > 120 * t clk ok l z z z l h h ok error l z z z l h h table 2 watchdog and clock supervision truth table the table assumes that no other error is detected, especially no undervoltage or overvoltage at the supply and regulator output.
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 29 2002-07 figure 11 watchdog violation reaction t 1 : no watchdog signals at wd1 or wd2 t 2 : normal operation. en is going high after the first watchdog edges at wd1 and wd2 are detected. t 3 : watchdog open window time exceeded: but below 120 *t clk (typ. 120 ms). error flag is not set. t 4 : watchdog time too short (below closed window time) t 5 : normal operation wd1 t en t wd2 t vr t sila t n sila t mr t t 1 t 2 t 3 t 4 t 5
tle 6210 tle 6211 block description and electrical characteristics v1.1 data sheet 30 2002-07 figure 12 logic diagram: detection of watchdog edges figure 13 block diagram watchdog logic 6 bit shift register q0 q1 q2 q3 q4 q5 wd resq clk & & 1 1 1 wd-detect ad06/02 clk j k c & 1 1 1 clk counter c r overvoltage at ust (active h) set error register 1 sets vr high ohmic; enq on 120 =15 d c q q ? 1 ? 1 1 undervoltage reset (low active) clk clk clk tle6210-wd-logic ad 04/02 d c r q q r q j k c q
tle 6210 tle 6211 application diagram v1.1 data sheet 31 2002-07 5 application diagram figure 14 application diagram linear regulator reset detection uzp uvlo and ovlo detection usts under- and overvoltage reset detection tle6210-app-diagram ad 11.7.02 ust usts uzp gnd res1 res2 en pgnd window watchdog sia mra wd1 wd 2 oscillator clock super- vision charge pump ucp supervisionlogic gnd c cp 68nf logic gnd power gnd u bat ust 5v from microcontroller from microcontroller from microcontroller from microcontroller to microcontroller to microcontroller to microcontroller pgnd sila pgnd nsila pgnd mr pgnd vr u bat u bat u bat u bat tle6210/1
tle 6210 tle 6211 package outlines v1.1 data sheet 32 2002-07 6 package outlines heatslug 1 10 110 i ndex marking does not include plastic or metal protrusion of 0.15 max. per side 1 x 45? (mold) 15.9 1) 0.15 a -0.2 (metal) 13.7 0 +0.1 +0.13 0.4 20 11 0.25 m a 1.27 1.2 -0.3 (heatslug) 15.74 0.1 (metal) 0.25 heatslug (mold) 20x 11 3.2 14.2 0.3 20 0.1 0.95 3.25 3.5 max. 0.1 1.3 0.1 -0.02 +0.07 6.3 0.25 0.15 2.8 11 1) b (metal) 5.9 b 0.1 0.15 5? 3? 1) p-dso-20-12 (plastic dual small outline package) gps05791 s orts of packing p ackage outlines for tubes, trays etc. are contained in our d ata book ?package information?. dimensions in mm s md = surface mounted device
tle 6210 tle 6211 package outlines v1.1 data sheet 33 2002-07
tle 6210 tle 6211 revision history v1.1 data sheet 34 2002-07 version date major changes v0.0 2002-07 advanced information data sheet tle 6210, tle 6211 device is a replacement of the tle 5200/tle 5201 with the following deviations form the specification from 1998-01-21. devices are only available in the p-dso-20-12 package or as bare dice the data sheet structure was changed and some chapters where moved. parameter reference numbers are changed now: tle 5200/01 tle 6210/11 control input sia 1.x 4.8.x control input mra 1.x 4.7.x enable 2.x 4.5.x reset outputs 3.x 4.10.x sila/nsila 4.x 4.8.x vr 5.x 4.6.x mr 5.x 4.7.x voltage supervision 6.x 4.9.x oscillator 7.x 4.2.x watchdog 8.x 4.11.x charge pump 9.x 4.3.x 5 v regulator 10.x 4.4.x general information 10.x 4.1.x absolute maximum ratings: digital i/os (reference m6, m7, m8) changed to -0.5 to 7 v v0.1 2001-11 update truth table v0.2 2002-04 increase error flag detection time t fsp from 112 clock cycles to 120 clock cycles (parameter 4.11.8) add of logic block diagram (figure 12) and watchdog timing diagrams (figure 5 to 10)
tle 6210 tle 6211 revision history v1.1 data sheet 35 2002-07 integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. characteristics show the deviation of parameter at the given supply voltage and junction temperature. typical values show the typical parameters expected from manufacturing. v1.0 2002-07 data sheet remove pad / chip information from the datasheet esd value sila, mr, vr,uzp 4kv update typ. value 4.3.3 extend and correct block description at chapters 4.4; 4.6; 4.7; 4.8 table 1: sila function at overtemperature changed table 2: timings as a function of t clk figure 11, t3: corect timing chapter 4.11: extend description; add figure 12: detection of watchdog edges appplciation diagram: replace free wheeling zener diodes at mr and vr relay by normal diodes. v1.1 2002-07 change device suffixes: bare dice: tle621x c packaged: tle621x g version date major changes
edition 2002-07 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2002. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. tle 6210 tle 6211 v1.1 data sheet 36 2002-07

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